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Semiconductor Electronics

Diodes, the Zener regulator and logic gates. Mostly reading a circuit or a truth table; transistors have not been asked in the recent papers.

Questions in the bank
145
q/paper in 2025–26
1.01
Numeric answer
16%
Notes pages
6

Tier: Core

When you’ll see it

A diode or Zener circuit, a doped semiconductor or p-n junction, or a network of logic gates with a truth table or waveform.

How this chapter is tested

This is a core chapter, set about once a paper. Logic gates are the largest group, and almost all of them are a drawn circuit: write each gate's output, simplify, then read off a gate, a truth table or a waveform.

Diodes, from the junction itself to the Zener regulator, take much of the rest, and they hold most of the numerical answers. Transistors have not been asked in the recent papers; that page is kept for revising the older ones.

Marks are lost on a direction: a battery read the wrong way round, a diode's bias judged by the sign of a voltage instead of which side is higher, or a Zener assumed to break down without checking. Once each diode is a wire or a break, the network is an ordinary circuit from Current Electricity.

The sub-skills

The distinct skills inside the chapter, in the order to learn them.

  • Semiconductors and the p-n junction

    Doping sets the majority carrier while n_e n_h = n_i² stays fixed; a junction is forward biased when its p-side is at the higher potential; LEDs, photodiodes and solar cells each use their own bias.

  • Diode circuits and rectifiers

    Decide each diode's bias, then treat it as a wire, a fixed drop or a break; a full-wave rectifier gives two pulses per input cycle.

  • Zener regulator

    Check breakdown first; then the load sits at V_Z, the series resistor takes the rest of the supply, and the Zener carries the series current less the load current.

  • Transistors and the CE amplifier

    I_E = I_B + I_C, α just under 1 and β large; voltage gain β R_L/r_i, and power gain β times that.

  • Reducing a gate network

    NAND and NOR are universal and a tied-input NAND is a NOT; use De Morgan's laws to reduce a network to one gate, or a constant.

  • Truth tables, waveforms and inputs

    Evaluate the reduced expression row by row, interval by interval, or backwards for the inputs that give a required output.

Traps to expect

Distractor shapes this chapter reuses. The Traps page covers the ones that cut across chapters.

  • Bias judged by sign

    p at −4 V and n at −9 V is forward biased. Compare the two potentials, not their signs.

  • The battery the wrong way round

    The long plate is positive. Reversing it flips every diode at once, and the flipped answer is usually an option.

  • Breakdown assumed

    If the divider voltage across the load is below V_Z, the Zener is off and the load voltage is not V_Z. Check before using it.

  • Tied inputs and bubbles

    A NAND with joined inputs is a NOT, and a bubble on an input inverts it first. Missing either makes the whole chain come out wrong.

Learn it before you drill it

This chapter has full teaching notes — foundations, worked examples, self-checks and a mastery check for each page. Read the notes once, then drill page by page below.

Semiconductor Electronics notes

Drill every Semiconductor Electronics question

145 questions from the bank, across 6 subtopics.

Drill the 145 questions

Drill one subtopic at a time

The 6 subtopics, in teaching order.

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